Design of 32-bit differential paired eFuse OTP memory in a form of two-dimensional array
来源期刊：中南大学学报(英文版)2012年第12期
论文作者：KIM Yoon-kyu JANG Ji-hye YOON Geon-soo LEE Dong-hoon HA Man-yeong HA Pan-bong KIM Young-hee
文章页码：3484 - 3491
Key words：eFuse; one-time programmable memory; 2-dimensional array
Abstract: A differential paired eFuse OTP (one-time programmable) memory cell which can be configured into a 2D (two-dimensional) eFuse cell array was proposed. The sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference voltage. With this 2D array of differential paired eFuse OTP memory cells, we design a 32-bit eFuse OTP memory IP. We use a sense amplifier based D F/F circuit as the BL (bit-line) SA (sense amplifier) and design a sensing margin test circuit with a variable pull-up load. It is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies.
KIM Yoon-kyu, JANG Ji-hye, YOON Geon-soo, LEE Dong-hoon, HA Man-yeong, HA Pan-bong, KIM Young-hee
(Department of Electronic Engineering, Changwon National University, 9 Sarim-Dong,
Changwon 641-773, Korea)
Abstract:A differential paired eFuse OTP (one-time programmable) memory cell which can be configured into a 2D (two-dimensional) eFuse cell array was proposed. The sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference voltage. With this 2D array of differential paired eFuse OTP memory cells, we design a 32-bit eFuse OTP memory IP. We use a sense amplifier based D F/F circuit as the BL (bit-line) SA (sense amplifier) and design a sensing margin test circuit with a variable pull-up load. It is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies.
Key words:eFuse; one-time programmable memory; 2-dimensional array
