简介概要

Multi-bit soft error tolerable L1 data cache based on characteristic of data value

来源期刊:中南大学学报(英文版)2015年第5期

论文作者:WANG Dang-hui LIU He-peng CHEN Yi-ran

文章页码:1769 - 1775

Key words:data cache; reliability; replica; data value; single event upset (SEU)

Abstract: Due to continuous decreasing feature size and increasing device density, on-chip caches have been becoming susceptible to single event upsets, which will result in multi-bit soft errors. The increasing rate of multi-bit errors could result in high risk of data corruption and even application program crashing. Traditionally, L1 D-caches have been protected from soft errors using simple parity to detect errors, and recover errors by reading correct data from L2 cache, which will induce performance penalty. This work proposes to exploit the redundancy based on the characteristic of data values. In the case of a small data value, the replica is stored in the upper half of the word. The replica of a big data value is stored in a dedicated cache line, which will sacrifice some capacity of the data cache. Experiment results show that the reliability of L1 D-cache has been improved by 65% at the cost of 1% in performance.

详情信息展示

Multi-bit soft error tolerable L1 data cache based on characteristic of data value

WANG Dang-hui(王党辉)1, LIU He-peng(刘合朋)1, CHEN Yi-ran(陈怡然)2

(1. School of Computer Science, Northwestern Polytechnical University, Xi’an 710072, China;
2. Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA 15261, USA)

Abstract:Due to continuous decreasing feature size and increasing device density, on-chip caches have been becoming susceptible to single event upsets, which will result in multi-bit soft errors. The increasing rate of multi-bit errors could result in high risk of data corruption and even application program crashing. Traditionally, L1 D-caches have been protected from soft errors using simple parity to detect errors, and recover errors by reading correct data from L2 cache, which will induce performance penalty. This work proposes to exploit the redundancy based on the characteristic of data values. In the case of a small data value, the replica is stored in the upper half of the word. The replica of a big data value is stored in a dedicated cache line, which will sacrifice some capacity of the data cache. Experiment results show that the reliability of L1 D-cache has been improved by 65% at the cost of 1% in performance.

Key words:data cache; reliability; replica; data value; single event upset (SEU)

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