J. Cent. South Univ. Technol. (2009) 16: 0621-0628

DOI: 10.1007/s11771-009-0103-6

Power management unit chip design for automobile active-matrix organic light-emitting diode display module

KIM J H¹, PARK J H¹, KIM J H¹, CAO T V¹, LEE T Y¹, BAN H J², YANG K², KIM H G², HA P B¹, KIM Y H¹

(1. Department of Electronic Engineering, Changwon National University, 9 Sarim-Dong,

Changwon 641-773, Korea;

2. Denso PS Electronics Corporation, 47 Seongsan-Dong, Changwon 641-315, Korea)

Key words:

DC-DC converter; AMOLED; charge pumping; power management unit (PMU); dual panel supply voltage；

1 Introduction

The flat-panel display (FPD) is used in hand-held devices like PDAs (personal digital assistant), cellular phones, digital cameras and media players, as well as automobile clusters [1]. TFT-LCD (thin film transistor-liquid crystal display) is used widely as automobile clusters. Recently, the OLED (organic light-emitting diode) display has been expanded incessantly. AMOLED (active-matrix OLED) is favorable for making it ultrathin and low-mass with advantages of wide viewing angle, excellent luminance, high power efficiency, and paper-thin thickness [2]. AMOLED display module consists of display panel, display driver IC (integrated circuit), and PMU (power management unit) supplying power supplies for the panel and the display driver IC. The PMU chips are classified into PMU chips with single panel supply voltage and PMU chips with dual panel supply voltage. The PMU chip with single panel supply voltage of 10 V has been already developed [3]. And the research on the PMU chip with dual panel supply voltage is going on nowadays.

VBP (9-16 V) and VCC (5 V) are used as input voltages, and ELVDD (5 V) and ELVSS (-6 V) are used as panel driving voltages. VCI (2.8 V) is used for the supply voltage of driver IC, and VDDI (1.8 V) is used for the interface as output voltages. There are four voltage regulators for VCI, VDDI, VLP (2.8 V), and ELVDD that generate internal supply voltages used in the chip from VBP of 9 to 16 V. VLP is used for a supply voltage to the level detector and the ring oscillator and ELVDD for a supply voltage to the AMOLED panel. And the reference bias generator generates reference voltages for VLP, ELVDD, ELVSS, VCI, and VDDI. Signals such as REF_ON, VLP_ON, ELVDD_ON, ELVSS_ON, VCI_ON, and VDDI_ON are used for turning on sequentially the reference bias generator, the voltage regulators, and the ELVSS generator. ELVDD of 5 V can be generated either by linearly-regulating the VBP voltage [4-5] or by using a buck converter [6-8] that is a type of switching regulator. On the other hand, ELVSS can be generated either by using a buck-boost converter supplying a negative voltage [9] or by using a DC-DC converter of charge-pumping type. Switching regulators of PWM (pulse width modulation) type using inductors are vulnerable to EMI (electro-magnetic interference) radiation and noise, and realize the limitations in miniaturization due to the use of discrete devices including the inductors. And many researches on the DC-DC converter of pumping type have been done for mobile devices using a battery voltage of 3.7 V [10-11]. For an automobile cluster with a battery voltage of 12 V, just a research on a positive charge pump boosting VDD of 10 V has been done. There is, however, no research on a PMU chip supplying dual panel supply voltage including a negative voltage of -6 V, and being designed as one chip.

A PMU chip supplying ELVDD, ELVSS, VCI, and VDDI for an 8.382 cm AMOLED panel used as an automobile cluster is designed as one chip to minimize

the power module of the cluster. A two-phase charge pump circuit using external pumping capacitor is proposed to increase its pumping current. A body-potential bias circuit [12] is used to eliminate the charge-loss problem springing up in pumping [13], and a simplified control clock switching between 0 V and VPP is used in the proposed charge pump circuit. A low- power start-up circuit used in the band-gap reference (BGR) voltage generator is proposed. A method with the logic power voltage VLP is used in the ELVSS power circuit to reduce the layout size of the ring oscillator. A PMU chip supplying dual panel power voltage is designed with MagnaChip’s 0.25 mm high-voltage process.

2 Circuit design

The designed PMU chip consists of reference bias generator and voltage regulator that supplies voltages VPP, VCI, ELVDD, VLP, and VDDI, and DC-DC converter that supplies voltage ELVSS, as shown in Fig.1. VBP and VCC are used as input voltages, and ELVDD, ELVSS, VCI, and VDDI are used as output voltages. There are four voltage regulators of VCI, VDDI, VLP, and ELVDD, which generate internal supply voltages used in the chip from VBP of 9 to 16 V. VLP is used as the supply voltage for the level detector and the ring oscillator in the ELVSS power circuit. And the reference bias generator generates reference voltages for VLP, ELVDD, ELVSS, VCI, and VDDI. Signals such as REF_ON, VLP_ON, ELVDD_ON, ELVSS_ON, VCI_ON, and VDDI_ON are used for turning on sequentially the reference bias generator, the voltage regulators, and the ELVSS generator.

Driving voltage ELVSS of an 8.382 cm AMOLED display panel requires a driving voltage of -6 V and a maximum driving current of over 50 mA. Fig.2 shows a

Fig.1 Block diagram of PMU chip

Fig.2 Simplified block diagram of DC-DC converter of charge pump type

DC-DC converter meeting the requirement, which consists of the BGR voltage generator, the ELVSS level detector, the ring oscillator, the control clock logic, the precharge circuit, and the single-stage charge pump. It is operated so that the output voltage ELVSS reaches the target value by using the negative feedback mechanism.

Charge pumps with an external pumping capacitor are usually based on H-tree charge pumps [14], as shown in Fig.3. Conventional negative charge pump circuit consists of external pumping capacitor C_P of 1 μF, charge reservoir capacitor C_R, NMOS (N-channel metal oxide semiconductor) transistor MN₁ that precharges node N₁ to GND (ground), inverter INV that makes node N₂ of the pumping capacitor switch between GND and VIN, and charge transfer switch MN₂ that transfers negative charge to VOUT when node N₂ switches from VBP to GND and voltage of node N1 becomes -VBP by capacitive coupling of capacitor C_P. When CLK₀ is VBP,

Fig.3 Conventional H-tree negative charge pump circuit

precharging transistor MN₁ turns on, and voltage of node N₁ precharges to GND. After this, voltage of node N₁ precharges to GND. After this, CLK₀ switches from VBP to VOUT and so MN₁ turns off. After this, CLK₁ switches from VOUT to VBP and voltage of node N₂ switches from VBP to GND, so voltage of node N₁ becomes -VBP from GND. Then, transistor MN₂ turns on and negative charge of transistor N₁ is transferred to node VOUT.

In case of the conventional charge pump circuit, the charge-loss problem that part of pumped charge drains off to deep N-well occurs since NPN BJT (bipolar junction transistor) parasitic to transistor MN₂ is in the active region when voltage of node N₁ switches from GND to -VBP. And CLK₀ and CLK₁ that turn on/off  transistors MN₁ and MN₂ are clock signals switching between VBP and VOUT (=ELVSS). MN1 and MN2 securely turn off when the levels of these clocks are VOUT.

The proposed ELVSS charge pump circuit uses four clock signals shown in Fig.4 and consists of precharge control circuit (MP₁, MN₁, MN₂, MP₂, MN₃ and MN₄) to precharge node N₁ to GND, cross-coupled NMOS charge transfer switches (MN₅ and MN₆), body potential biasing circuit, external pumping capacitors (C₁ and C₂), and external charge reservoir capacitor C_R. The timing diagram of the ELVSS charge pump in the steady state is shown in Fig.5. At t₄ when CLK₀ is 0 V, voltage of node G₂ becomes VBP, MN₁ turns on and voltage of node ND₁ precharges to 0 V for the circuit consisting of MP₁, MN₁,

Fig.4 Proposed two-phase ELVSS charge pump circuit

and MN₂ of the precharge control circuit. When CLK₁ switches from 0 V to VBP, voltages of nodes ND₁ and G₂ are all -VBP by capacitive coupling of C₁. At t₀ when CLK₃ is 0 V, voltage of node G₁ becomes VBP, MN₃ turns on, and voltage of node ND₂ precharges to 0 V. When CLK₃ is VBP, voltages of nodes ND₂ and G₁ become -VBP by capacitive coupling of C₂ with MN₄ turned on, as shown in Fig.5. When voltages of nodes ND₁ and ND₂ switch to -VBP and 0 V by capacitive coupling of C₁ and C₂, respectively, MN5 turns on and MN6 turns off. Thus, negative charge transfers to node ELVSS through MN₅. When voltages of nodes ND₂ and ND₁ switch to -VBP and 0 V, respectively, MN₆ turns on and MN₅ turns off. Thus, negative charge of node N₂ transfers to node ELVSS through MN₆, and negative charge pumping occurs twice per cycle, as shown in Fig.5. And the pumping current of ELVSS charge pump is increased by proposing a two-phase charge pump of Fig.4 instead of a single-phase charge pump of Fig.3.

Fig.6 shows the BGR voltage generator circuit. As

Fig.5 Timing diagram of ELVSS charge pump in steady state

Fig.6 Band-gap reference (BGR) voltage generator circuit

can be seen in Eqn.(1), reference current I_ref (=2I) consists of two terms. One term with V_T (thermal voltage) increases with the increase of temperature and the other term with V_EB (emitter-base voltage) decreases with the increase of temperature. Thus, the reference current is insensitive to PVT variations [15] and the reference voltage V_ref on R₃ is also insensitive to PVT (process voltage temperature) variations.

                   (1)

          (2)

where  N (=10) is the ratio of area of PNP BJT emitter Q₁ to that of Q₂.

As can be seen in Fig.7, voltage of node N₁ is VBP-2(|V_TP|+|V_DSAT|) in the conventional start-up circuit. Since voltage of node N₁ increases with the increase of the battery supply voltage VBP, current flowing through MN₃ also increases. And the current flowing through MP₃ also increases since the voltage difference between the source and the gate increases. New start-up circuit of Fig.8 is proposed to enhance this kind of current increase at high-voltage VBP. In case of the proposed start-up circuit, the current flowing through MN₃ decreases since the drain node voltage of MN₃ decreases by inserting N PMOS (P-channel metal oxide semiconductor) diodes between node N₁ and drain node of MN₃. And the current flowing through MP₃ decreases since the current flowing through MN₃ decreases, and |V_DSAT| decreases. So the voltage difference between the source and the gate of MP₃ decreases.

Fig.7 Conventional start-up circuit

Fig.9 shows a proposed ELVSS level detector outputting OSC_ENb of 0 V that enables the ring oscillator of Fig.2 and the negative charge pumps if |ELVSS/3| is lower than VREF_ELVSS. Thus, voltage ELVSS falls in the negative direction. The ELVSS level detector uses logic supply voltage VLP and PMOS differential pair of the comparator uses logic transistors. Reliability of the logic devices used in the comparator is secured by discharging node N₁ to 0 V with signals ELVSS_EN and ELVSS_ENb in entering stand-by mode.

Fig.8 Proposed start-up circuit

The ring oscillator either oscillates if the ELVSS_ENb signal from the level detector of Fig.9 is  0 V or stops if the ELVSS_ENb signal from the level detector of Fig.9 is VLP. If voltage VBP is used as the supply voltage to the ring oscillator, the ring oscillator should be designed with high-voltage devices and its layout area should be increased to meet a long oscillation period of 100 ms. Fig.10 shows a proposed ring oscillator of which layout area is decreased since it is designed with logic devices by supplying the logic power supply VLP to the ring oscillator. Fig.10 shows a VLP-to-VBP level translator of which the purpose is to translate the switching voltage VLP, that is, output signal OSC_ELVSS from the ring oscillator to VBP.

Fig.11 shows the voltage regulator circuit that supplies logic supply voltage VLP of the proposed DC-DC converter. VBP is used as input voltage of the charge pump, driving voltage ELVDD of the AMOLED panel, input voltage VCI of the OLED display driver IC, and voltage VDDI of the interface. Voltage regulator circuit regulates in the steady state such that V_ref is equal to V_reg/(N+1). Therefore, V_reg becomes (1+N)V_ref.

3 Simulation results

Fig.12 shows the simulation results of on-current of the BGR circuit with respect to battery power supply VBP when simulation is performed under the condition

Fig.9 Proposed ELVSS level detector circuit

Fig.10 Proposed ring oscillator circuit

Fig.11 Proposed voltage regulator circuit

of fast transistor model and temperature of -40 ℃. This shows that the on-current of the proposed BGR is 42% lower than that of the conventional counterpart.

Fig.13 shows the simulation results of pumping current with respect to the oscillation period for the designed ELVSS charge pump when SPICE simulation is

Fig.12 On-current IBP vs VBP of BGR

done under the condition of slow transistor model, VBP=9 V and temperature of 90 ℃. As shown in Fig.13, the pumping current I_ELVSS of the ELVSS charge pump is 52.11 mA at the oscillation period of 100 ms as a simula-

Fig.13 Pumping current of designed ELVSS charge pump with respect to oscillation period

tion result, which almost approaches 60 mA that is I_ELVSS under the ideal condition and is larger than the loading current of 50 mA at the panel. The capacitances of the external pumping capacitors C₁ and C₂ of the ELVSS charge pump in Fig.4 are 1 mF. The oscillation period of the ring oscillator is designed to be 100 ms. I_ELVSS under the ideal condition is calculated according to Eqn.(3) and the pumping current of the two-phase charge pumping scheme is twice larger than that of the single-phase counterpart.

×2=×2=60 mA               (3)

where  C_p is the capacitance of the external pumping capacitors C₁ and C₂, here it equals 1 μF.

Fig.14 shows simulation results of power-on

Fig.14 Output voltage sequence of designed DC-DC converter

sequence for the designed DC-DC converter when simulation is done under the condition of slow transistor model, VBP=9 V and temperature of 90 ℃.

A PMU chip supplying dual panel supply voltage for an 8.382 cm AMOLED display module is designed with MagnaChip’s 0.25 mm high-voltage process. The layout area is 460 mm ×840 mm.

4 Conclusions

(1) A PMU chip supplying dual panel supply voltage for an 8.382 cm OLED display module is designed with MagnaChip’s 0.25 mm high-voltage process. The designed PMU chip supplies ELVDD, ELVSS, VCI, and VDDI.

(2) The designed two-phase charge pump circuit using external charge pumping capacitor can drive a current of more than 50 mA required for the AMOLED panel.

(3) The power consumption of the start-up circuit is 42% smaller since a low-power technique is applied to the start-up circuit of the band-gap reference voltage generator.

(4) The layout size is reduced since logic supply voltage is used for the ring oscillator instead of the battery power supply. The layout size of the designed PMU chip is 477 mm×653 mm.

(5) The PMU chip with dual panel supply voltage is the best solution for the AMOLED display module requiring both low EMI characteristic and miniaturization.

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(Edited by CHEN Wei-ping)

Received date: 2008-10-20; Accepted date: 2009-03-02

Corresponding author: KIM Y H, Professor, PhD; Tel: +82-55-285-1023; E-mail: youngkim@changwon.ac.kr