Virtual reconfigurable architecture for evolving combinational logic circuits

WANG Jin(王进)^{1, 2}, LEE Chong-Ho²

(1. Chongqing Key Laboratory of Computational Intelligence
(Chongqing University of Posts and Telecommunications), Chongqing 400065, China;
2. Department of Information & Communication Engineering, Inha University, Incheon 402-751, Korea)

Abstract:A virtual reconfigurable architecture (VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level. The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect (PCI) board with an Xilinx Virtex xcv2000E field programmable gate array (FPGA). To improve the quality of the evolved circuits, the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit. To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning, a self-adaptive mutation rate control (SAMRC) scheme is introduced. In the evolutionary process, the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations. The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function, a 2-bit multiplier, and a 3-bit multiplier. The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort, when compared to the existing evolvable hardware approaches.

Key words:evolutionary algorithm; evolvable hardware; self-adaptive mutation rate control; virtual reconfigurable architecture